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3A, 1MHz, Low-Voltage, Step-Down Regulators with
Synchronous Rectification and Internal Switches
Table 1. Recommended Component Values (I OUT = 3.0A)
V IN (V)
5
5
5
5
5
3.3
3.3
3.3
3.3
V OUT (V)
3.3
2.5
1.8
1.5
1.1
2.5
1.8
1.5
1.1
f PWM (kHz)
800
865
850
860
625
570
850
860
680
L (μH)
2.2
2.2
2.2
2.2
2.2
1.5
1.5
1.5
1.5
R TOFF (k ? )
39
56
75
82
130
39
51
62
100
device operates in discontinuous conduction. Current-
sense circuitry monitors the current through the NMOS
synchronous switch, turning it off before the current
reverses. This prevents current from being pulled from
the output filter through the inductor and NMOS switch to
ground. As the device switches between operating
modes, no major shift in circuit behavior occurs.
MAXIMUM RECOMMENDED
OPERATING FREQUENCY vs. INPUT VOLTAGE
1400
V OUT = 1.5V
1200
1000
100% Duty-Cycle Operation
When the input voltage drops near the output voltage,
the duty cycle increases until the PMOS MOSFET is on
continuously. The dropout voltage in 100% duty cycle
is the output current multiplied by the on-resistance of
the internal PMOS switch and parasitic resistance in the
inductor. The PMOS switch remains on continuously as
800
600
400
200
V OUT = 1.8V
V OUT = 2.5V
V OUT = 3.3V
long as the current limit is not reached.
0
2.6
3.1
3.6
4.1
4.6
5.1
5.6
Internal Digital Soft-Start Circuit
Soft-start allows a gradual increase of the current-limit
level at startup to reduce input-surge currents. The
MAX1830/MAX1831 contain internal digital soft-start cir-
cuits, controlled by a counter, a digital-to-analog con-
verter (DAC), and the current-limit comparator. At
power-on or in shutdown mode, the soft-start counter is
reset to zero. When the MAX1830/MAX1831 are enabled
or powered up, its counter starts counting LX switching
cycles, and the DAC begins incrementing the compari-
son voltage applied to the current-limit comparator. The
DAC ramps up the internal current limit in four 25%
steps, as the count increases to 256 cycles. As a result,
the main output capacitor charges up relatively slowly.
The exact time of the output rise depends on nominal
switching frequency, output capacitance, and the load
current, and is typically 1ms.
Shutdown
Drive SHDN to a logic-level low to place the
MAX1830/MAX1831 in low-power shutdown mode and
V IN (V)
Figure 3. Maximum Recommended Operating Frequency vs.
Input Voltage
reduce supply current to less than 1μA. In shutdown, all
circuitry and internal MOSFETs turn off, and the LX
node becomes high impedance. Drive SHDN to a
logic-level high or connect to V CC for normal operation.
Summing Comparator
Three signals are added together at the input of the
summing comparator (Figure 2): an output-voltage error
signal relative to the reference voltage, an integrated
output-voltage error correction signal, and the sensed
PMOS switch current. The integrated error signal is pro-
vided by a transconductance amplifier with an external
capacitor at COMP. This integrator provides high DC
accuracy without the need for a high-gain amplifier.
Connecting a capacitor at COMP modifies the overall
loop response (see Integrator Amplifier ).
8
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